![]() Traditionally, application specific integrated circuit (ASIC) devices have been used in the integrated circuit (IC) industry to reduce cost, enhance performance or meet space constraints. having at least two inputs acting on one output Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form H03K19/1737- Controllable logic circuits using multiplexers.H03K19/1733- Controllable logic circuits.having at least two inputs acting on one output Inverting circuits using specified components using elementary logic circuits as components having at least two inputs acting on one output Inverting circuits using specified components having at least two inputs acting on one output Inverting circuits Status Active legal-status Critical Current Anticipated expiration legal-status Critical Links LTD., LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). ![]() Assignors: MADURAWE, RAMINDA U Publication of US20070171105A1 publication Critical patent/US20070171105A1/en Application granted granted Critical Publication of US7336097B2 publication Critical patent/US7336097B2/en Priority to US12/480,213 priority patent/US7656190B2/en Assigned to TIER LOGIC, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Priority claimed from US10/743,894 external-priority patent/US7019557B2/en Priority claimed from US11/355,931 external-priority patent/US7176716B2/en Priority to US11/728,839 priority Critical patent/US7336097B2/en Application filed by Tier Logic Inc filed Critical Tier Logic Inc Assigned to VICICIV TECHNOLOGY, INC. Original Assignee Tier Logic Inc Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) ( en Inventor Raminda Udaya Madurawe Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Active Application number US11/728,839 Other versions US20070171105A1 Google Patents Look-up table structure with embedded carry logicÄownload PDF Info Publication number US7336097B2 US7336097B2 US11/728,839 US72883907A US7336097B2 US 7336097 B2 US7336097 B2 US 7336097B2 US 72883907 A US72883907 A US 72883907A US 7336097 B2 US7336097 B2 US 7336097B2 Authority US United States Prior art keywords lut inputs data logic carry Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. ![]() Google Patents US7336097B2 - Look-up table structure with embedded carry logic US7336097B2 - Look-up table structure with embedded carry logic ![]()
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